The present invention relates to memory systems, and more particularly to read bitline inhibit during multilevel cell voltage mode sensing.
Memory systems include memory arrays that include a plurality of memory cells arranged in rows and columns. Row of memory cells are coupled to corresponding source lines which are selected by decoder circuitry. Columns of memory cells are coupled to corresponding bitlines which are used for reading the content of the selected row of memory cells. Resistances on the source line and capacitances on the bitline create local source line voltage offsets. In some instances, the offsets may create a data pattern dependency for reading of the multilevel memory cells.